AdeptChip Services is a full service IC design firm offering team augmentation and turnkey solutions for end-to-end chip design. Company is dedicated to offering a one-stop solution for VLSI chip design needs. Our engineers are capable of delivering solutions from Concept to Silicon. We specialize in providing onsite support for mission critical tapeout tasks such as power integrity, timing closure and chip finishing.
Our biggest strength lies in extensive hands-on experience of taping out multi-million gate designs and working on advanced process nodes (14,16, 22, 28, 32, 40, 45, 65, 90, 130, 180nm).
We have a proven track record of taping out designs with complexities ranging from 40M to 100M gate-count and in various technologies 10nm, 14nm, 16nm, 28nm, 32nm, 45nm and 65nm. The flows that have been used in implementing these chips vary based on the complexity and nature of the design. We are good at taking designs and optimizing area and coming-up with best-bounding box for the chip and coordinating with package-team for better package & aspect-ratio of the chip. This will result in optimized “GDPW” (Gross dies per wafer).
o SoC Verification
o IP / SubSystem Verification
o Random Verification with SV-UVM
Design For Test (DFT)
o Scan Insertion
o ATPG Pattern Generation & Simulation
o Flat fullchip implementation (Netlist to GDSII)
o Hierarchical fullchip implementation (Netlist to GDSII)
o Block level implementation (Netlist to GDSII)