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1 Opening

Posted 1 month, 3 weeks Back

SalarySalary

7Lac  - 45Lac  PM

ExperienceExperience

Freshers can Apply| Resume Required

LocationLocation

Indiranagar, Bengaluru

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Additional Details

Job Type

Full Time

Shift Timings

9:30 AM - 6:30 PM(day shift)

Working Days

5 days

Job Requirements

Education

Below 10th allowed

Experience

Freshers as Embedded / VLSI / ASIC / Chip Design preferred

Age

18 - 60 yrs

Job Description

•            Independent planning and execution of Netlist-to-GDSII.

•            Full exposure to all aspects of design flows like floor planning, placement, CTS, routing, crosstalk avoidance, physical verification.

•            Should have good exposure to high frequency design convergence and exposure to physical design methodology.

•            1+ years of experience in IC design Experience in leading block level or chip level Timing closure & Physical Design activities. Work independently in the areas of RTL to GDSII implementation.

•            Ability to collaborate and resolve issues wrt constraints validation, verification, STA, Physical design, etc.

•            Knowledge of low power flow (power gating, multi-VT flow, power supply management etc.).

•            Circuit level comprehension of time critical paths in the design. Tcl/Perl scripting.

•            Willing to handle technical deliveries with a small team of engineers.

•            Well versed with the level timing closure (STA), timing closure methodologies, ECO generation and predictable convergence.

•            Well versed with parasitic extraction, LVS/DRC and other Physical verification checks.

•            Should be able to provide clear directions to the team wrt PNR issues.

•            Drive methodology with help of local and external CAD/EDA teams for faster design convergence.

•            Well aware of place and route methodologies and hands on experience with timing convergence.

•            Qualification: Strong problem-solving skills and teamwork, Self-motivated, excellent verbal and written communication. Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)

Company Details

Company Logo

product based company(Posted by product based company)

Corporate|Banking / Financial Services / Insurance|500-1000 Employees

product based company and also they are having their own product

Physical Verification

at  product based company(Posted by product based company)

Salary

7Lac  - 45Lac  PM

Location

Indiranagar, Bengaluru

Experience

Freshers can Apply

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