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60 Openings

Posted 5 months, 2 weeks Back


7Lac  - 45Lac  PM


3 yrsto18 yrs experience| Resume Required


HITEC City, Hyderabad

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Additional Details

Job Type

Full Time

Shift Timings

9:30 AM - 6:30 PM(day shift)

Working Days

5 days

Job Requirements


Below 10th allowed


3 yrs to 18 yrs of experience as Embedded / VLSI / ASIC / Chip Design mandatoryCompulsory


18 - 60 yrs

Job Description

•            Hands on experience with FPGA design tools: Simplify, Vivado, XILINX ISE, 

•            Work experience in Xilinx FPGA based design implementation.

•            FPGA RTL coding(Verilog/VHDL/System Verilog), FPGA constraint setup, verification, synthesis, par and timing closure.

•            Hands-on experience in WIFI/Ethernet/PCIe/USB/Multimedia/UFS/ARM CPU/DDR3/DDR emulation.

•            Familiar with hardware schematics and Lab tools to debug.


•            Interact with software/Verification team to resolve FPGA related technical implementation and integration issues.

•            Work closely with other RTL Design/Validation and Software teams for bug/issue debug, support and build bring up in emulation platform.


Company Details

Company Logo

product based company(Posted by product based company)

Corporate|Banking / Financial Services / Insurance|500-1000 Employees

product based company and also they are having their own product

RTL/FPGA design engineer

at  product based company(Posted by product based company)


7Lac  - 45Lac  PM


HITEC City, Hyderabad


3 yrsto18 yrs experience

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