Senior Engineer - DFT

Wafer Space
Bengaluru - Koramangala
15,00,000 - 30,00,000
/ monthly
Salary benefits
Requirements
5 - 8 years experience
Graduate
25 - 40 years
No gender preference
Shift timings
Working days
5 days/week
Week offs
SATURDAY, SUNDAY
Morning Shift
10:00am - 7:00pm

Job description

Candidate must have handled scan insertion, pattern generation & simulations (timing sims), debug, handled different ATPG tools and flows, understand scan compression flows.

Should understand controllability and observability concepts, should understand why DFTcoverage is important and how to improve coverage.

Ideal candidate should have done DFT architecture and planning for a full chip, by himself.

Good to have shell scripting /Perl/Python/Tcl experience for productivity improvement.

Usage of functional test patterns to improve test coverage, analog blocks test exposure not necessary but good to have.

Good to have exposure to post-silicon debug & industry level ATE exposure

Cadence tools and flows - Genus, Modus - good to have

Good to have fair understanding of boundary scan and memory BIST

Additional Requirements
Experience
Embedded / VLSI / ASIC / Chip Design
Job Type
Full Time
Skills
ATPG
Scan
Coverage analysis
LBIST
Other requirements
- DFT architecture and planning for a full chip
- shell scripting /Perl/Python/Tcl experience for productivity improvement.
- sound technical background in DFT concepts
- Scan, ATPG, Coverage analysis, LBIST,
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Posted on 02 Jan 2020
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Embedded / VLSI / ASIC / Chip Design in Wafer Space