SalarySalary

15Lac  - 30Lac  CTC

ExperienceExperience

8 yrsto12 yrs experience| Resume Required

LocationLocation

Koramangala, Bengaluru

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Company Typically replies in 4 d

Additional Details

Job Type

Full Time

Shift Timings

10:00 AM - 7:00 PM(day shift)

Working Days

5 days|Off Days:Saturday,Sunday

Job Benefits

PF & ESIC

Job Requirements

Education

Graduation degree preferred

Experience

8 yrs to 12 yrs of experience as Embedded / VLSI / ASIC / Chip Design mandatoryCompulsory

shell scripting /Perl/Python/Tcl experience for productivity improvement.Compulsory

Should know 1149.1 and 1149.6 IEEE standardsCompulsory

Full chip testability and coverageCompulsory

Scan, ATPG, Coverage analysis, LBIST,Compulsory

BSCAN (optional), MBIST (optional)

Age

25 - 45 yrs

Others

Expected SalaryCompulsory

Notice PeriodCompulsory

Job Description

Candidate must have handled scan insertion, pattern generation & simulations (timing sims), debug, handled different ATPG tools and flows, understand scan compression flows.

Should understand controllability and observability concepts, should understand why DFT coverage is important and how to improve coverage.

Ideal candidate should have done DFT architecture and planning for a full chip, by himself.

Usage of functional test patterns to improve test coverage, analog blocks test exposure not necessary but good to have.

Good to have shell scripting /Perl/Python/Tcl experience for productivity improvement.

Good to understand boundary-scan concepts and worked hands-on with JTAG tools. Should know 1149.1 and 1149.6 IEEE standards

Good to have knowledge of reparable memories, MBIST algorithms. MBIST - controller generation, integration at block and top level, pattern gen & simulations.

Good to have exposure to post-silicon debug & industry level ATE exposure

Cadence tools and flows - Genus, Modus - good to have


Company Details

Wafer Space was founded with the ideals of providing true value in Product Engineering Services to all our clients. Wafer Space is focused in the domains of Semiconductor and Automotive. Our world class engineering team with its intensive knowledge in Chip Design, Automotive embedded software and Embedded product design combined with our ability to execute complex turnkey projects with a steadfast focus on quality is what differentiates us.
Wafer Space has one of the industry’s most rigorous selection criteria for engineers which results in a world class engineering team. We strongly believe in continuous learning and growth for all employees. Our organizational culture nurtures creativity and innovation amongst our team players as work no longer is a chore, it’s what we have fun doing!
Wafer Space has design centers in Bangalore and Pune India and San Jose, CA, USA. With our proactive client and employee model, Wafer Space is well positioned to deliver quality and timely services to our clientele in Semiconductor and Automotive.

Wafer Space Expertise

• Semiconductor
       •    RTL Design and Verification
       •    Physical Design and DFT
       •    Turnkey SOC Execution from RTL to GDSII
       •    Custom Verification IP Development
       •    Analog Design, Layout and Verification

•    Automotive
       •    Product Areas
               •    ADAS
               •    Infotainment
               •    Connectivity
               •    Body Electronics
               •    Safety and Access
               •    BMS

       •    Services
               •    Requirements Engineering
               •    Software Development
               •    Verification and Validation
               •    Rapid Prototyping

Tech Lead - DFT

at  Wafer Space Semiconductor Technologies Private Limited(Posted by wafer space)

Salary

15Lac  - 30Lac  CTC

Location

Koramangala, Bengaluru

Experience

8 yrsto12 yrs experience

Company Typically replies in 4 d

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