Candidate must have handled scan insertion, pattern generation & simulations (timing sims), debug, handled different ATPG tools and flows, understand scan compression flows. |
Should understand controllability and observability concepts, should understand why DFT coverage is important and how to improve coverage. |
Ideal candidate should have done DFT architecture and planning for a full chip, by himself. |
Usage of functional test patterns to improve test coverage, analog blocks test exposure not necessary but good to have. |
Good to have shell scripting /Perl/Python/Tcl experience for productivity improvement. |
Good to understand boundary-scan concepts and worked hands-on with JTAG tools. Should know 1149.1 and 1149.6 IEEE standards |
Good to have knowledge of reparable memories, MBIST algorithms. MBIST - controller generation, integration at block and top level, pattern gen & simulations. |
Good to have exposure to post-silicon debug & industry level ATE exposure |
Cadence tools and flows - Genus, Modus - good to have |